Designers and manufacturers of electronic systems continually seek methods for increasing the speed and efficiency of electronic circuits. One method for increasing system efficiency and speed is to integrate as much of the system as possible into a single CMOS integrated circuit (IC). A well-designed CMOS IC chip increases the noise immunity of internal signals. Such high-level integration also increases the speed and efficiency of the IC chip, because signals have less distance to travel.
In a binary logic circuit for implementing a logic function, inputs and outputs of the logic function are generally represented as either a high logic level (i.e., a "1") or a low logic level (i.e., a "0"). FIG. 1 is a graphical illustration of the relationship in a binary logic circuit between a high reference voltage threshold (VREFH), a low reference voltage threshold (VREFL), and voltage levels recognized by a logic circuit with respect to these voltages. Thus, as shown in FIG. 1, a "1" is detected, and a signal is said to be in a valid high state, whenever the signal is equal to or above the high reference voltage threshold defined by VREFH. Likewise, a "0" is detected, and a signal is said to be in a valid low state, whenever the signal is equal to or below the low reference voltage threshold defined by VREFL. However, when the input signal is transitioning from one state to another (i.e., when the input signal is above the low reference voltage threshold VREFL, but below the high reference voltage threshold VREFH), it is not recognized as valid and is said to be "floating".
In a binary digital system, the specific voltage levels defined by VREFH and VREFL may vary depending upon the family of components used, the process used, and the specific application. For example, in transistor-transistor logic (TTL), VREFH is typically +2.0 volts and VREFL is typically +0.8 volts. Likewise, for CMOS logic components, VREFH is typically +3.3 volts and VREFL is typically +0.7 volts (assuming a +5.0 volt supply). For ECL logic components, VREFH is typically -1.105 volts and VREFL is typically -1.475 volts.
Today, logic circuits are commonly implemented in CMOS. However, as illustrated in FIG. 1, the voltage swing required to change a signal from logic "0" to logic "1" or vice versa is at least 2.6 V.
The switching time of a logic gate can be improved by decreasing the voltage swing required of a logic component. For example, ECL logic components only require a voltage swing of approximately 0.37 V to change signal from logic "0" to logic "1" or vice versa. The switching time is much faster for ECL logic components than for CMOS logic components because it takes far less time to pull a voltage level on a component 0.37 V than it does to pull a voltage level 2.6 V. However, despite the faster switching speeds of ECL components, ECL logic is not typically used in integrated circuits due to the greater power consumption of ECL components. In other words, the cost of providing low voltage swings (and hence faster switching speeds) is greater power consumption. Furthermore, CMOS and ECL logic components cannot be combined on the same IC chip because they are fabricated using different processes.
Accordingly, it would be desirable to provide a family of fast CMOS logic gates which could be integrated into a CMOS logic circuit in speed critical paths. Moreover, it would be desirable to implement such a family of fast CMOS logic gates using a generic logic cell which could be configured in a number of ways to provide for different logic functions. The use of a generic logic cell would enable designers to easily predict delay times and circuit loads for a given logic path.